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products and specifications discussed herein ar e subject to change by micron without notice. 256mb: x16, x32 mobile ddr sdram features pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__1.fm - rev. h 6/08 en 1 ?2005 micron technology, inc. all rights reserved. mobile ddr sdram mt46h16m16lf ? 4 meg x 16 x 4 banks mt46h8m32lf/lg ? 2 meg x 32 x 4 banks for the latest data sheet, refer to micron?s web site: www.micron.com features ?v dd/ v dd q = 1.70?1.95v ? bidirectional data strobe per byte of data (dqs) ? internal, pipelined double data rate (ddr) architecture; two data accesses per clock cycle ? differential clock inputs (ck and ck#) ? commands entered on each positive ck edge ? dqs edge-aligned with data for reads; center- aligned with data for writes ? four internal banks for concurrent operation ? data masks (dm) for masking write data?one mask per byte ? programmable burst lengths: 2, 4, or 8 ? concurrent auto precharge option supported ? auto refresh and self refresh modes ? 1.8v lvcmos compatible inputs ? on-chip temperature sensor to control self refresh rate ? partial-array self refresh (pasr) ? deep power-down (dpd) ? selectable output drive (ds) ? clock stop capability ? 64ms refresh period table 1: configuration addressing dq bus width architecture jedec- standard option reduced page-size option number of banks 44 bank address balls ba0, ba1 ba0, ba1 x16 row address balls a0?a12 ? column address balls a0?a8 ? x32 row address balls a0?a11 a0?a12 column address balls a0?a8 a0?a7 notes: 1. only available for x16 configuration. 2. only available for x32 configuration. table 2: key timing parameters speed grade clock rate (mhz) access time cl = 2 cl = 3 cl = 2 cl = 3 -6 83.3 166 6.5ns 5.0ns -75 83.3 133 6.5ns 6.0ns options marking ?v dd /v dd q ? 1.8v/1.8v h ? configuration ? 16 meg x 16 (4 meg x 16 x 4 banks) ? 8 meg x 32 (2 meg x 32 x 4 banks) 16m16 8m32 ?row size option ? jedec-standard option lf ? reduced page-size option 2 lg ? plastic ?green? packages ? 60-ball vfbga 8mm x 9mm 1 ? 90-ball vfbga 8mm x 13mm 2 bf b5 ? timing ? cycle time ? 6ns at cl = 3 ? 7.5ns at cl = 3 -6 -75 ?power ? standard ? low i dd 2p/i dd 6 none l ? operating temperature range ? commercial (0c to +70c) ? industrial (?40c to +85c) none it ?design revision :a
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lftoc.fm - rev. h 6/08 en 2 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 fbga part marking decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 functional block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 ballouts and ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 standard mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 operating mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 temperature-compensated self refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 partial-array self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 output driver strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 stopping the external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 deep power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 bank/row activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 truncated reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 deep power-down (dpd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lflof.fm - rev. h 6/08 en 3 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram list of figures list of figures figure 1: 256mb mobile ddr part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 2: functional block diagram (16 meg x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: functional block diagram (8 meg x 32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 4: 60-ball vfbga ball assignments ? 8mm x 9mm (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: 90-ball vfbga ball assignments ? 8mm x 13mm (top view ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 6: standard mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 8: extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 9: clock stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 10: mobile dram state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 11: activating a specific row in a specific bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 12: example: meeting t rcd ( t rrd) min when 2 < t rcd ( t rrd) min . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 13: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 14: read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 15: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 16: nonconsecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 17: random read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 18: terminating a read bu rst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 19: read-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 20: read-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 21: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 22: write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 23: consecutive write-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 24: nonconsecutive write-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 25: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 26: write-to-read ? uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 27: write-to-read ? interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 28: write-to-read ? odd number of data, interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 29: write-to-precharge ? uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 30: write-to-precharge ? interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 31: write-to-precharge ? odd number of data, interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 32: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 33: power-down command (in active or precharge modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 34: deep power-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 35: deep power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 36: typical self refresh current vs. temperature (x16, x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 37: data output timing ? tdqsq, tqh, and data valid wind ow (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 38: data output timing ? tdqsq, tqh, and data valid wind ow (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 39: data output timing ? tac and t dqsck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 40: data input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 41: initialize and load mode regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 42: power-down mode (active or prec harge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 43: auto refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 44: self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 figure 45: bank read ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 figure 46: bank read ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 47: bank write ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 figure 48: bank write ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 figure 49: write ? dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 figure 50: 60-ball vfbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 figure 51: 90-ball vfbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lflot.fm - rev. h 6/08 en 4 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram list of tables list of tables table 1: configuration addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: 60-ball vfbga ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 4: 90-ball vfbga ball description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 5: burst definition table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 6: partial-array self refresh options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 7: truth table ? commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 8: truth table ? dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 9: truth table ? cke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 10: truth table ? current state bank n ? command to bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 11: truth table ? current state bank n ? command to bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 12: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 13: electrical characteristics and oper ating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 14: capacitance (x16, x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 15: i dd specifications and conditions (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 16: i dd specifications and conditions (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 17: i dd 6 specifications and conditions (x16, x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 18: electrical characteristics and re commended ac operating conditions . . . . . . . . . . . . . . . . . . . . . . .61
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 5 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram fbga part marking decoder figure 1: 256mb mobile ddr part numbering fbga part marking decoder due to space limitations, fbga-packaged components have an abbreviated part marking that is different from the part number. for a quick conversion of an fbga code, see the fbga part marking decoder at www.micron.com/decoder. general description the 256mb mobile ddr sdram is a high -speed cmos, dynamic random-access memory containing 268,435,456 bits. it is in ternally configured as a quad-bank dram. on the x16 device, each of the 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. on the x32 device, each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32 bits. the 256mb mobile ddr sdram uses a double da ta rate architecture to achieve high- speed operation. the double data rate architecture is essentially a 2 n -prefetch architec- ture with an interface designed to transfer two data words per clock cycle at the i/o balls . a single read or write access for the 256mb mobile ddr sdram effectively consists of a single 2 n -bit-wide, one-clock-cycle data tran sfer at the internal dram core and two corresponding n -bit-wide, one-half-clock-cycle data transfers at the i/o balls . a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a st robe transmitted by the mobile ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the x16 offering has two data strobes: one for the lower byte and one for th e upper byte. the x32 offering has four data strobes, one per byte. example part number: m t46h16m16lfxx-75it :a micron ddr mt46 mobile configuration package revision speed temp ? v dd / v dd q v dd /v dd q 1.8v/1.8v h configuration 16 meg x 16 16m16lf 8 meg x 32 8m32lf package 60-ball vfbga (lead-free) bf 90-ball vfbga (lead-free) b5 speed grade -6 t ck = 6.0ns -75 t ck = 7.5ns -10 t ck = 9.6ns operating temp commercial it industrial revision :a first generation
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 6 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram general description the 256mb mobile ddr sdram operates from a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dq s, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the mobile ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coin- cident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting co lumn location for the burst access. the mobile ddr sdram provides for programmable read or write burst lengths of 2, 4, or 8. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdr sdram, the pipeline d, multibank architecture of mobile ddr sdram enables concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a power-saving power-down mode. deep power-down mode is offered to achieve maximum power reduction by eliminating the power draw of the memory array. data will not be retained when the device enters dpd mode. self refresh mode offers temperature compensation through an on-chip temperature sensor and partial-array self refresh, whic h enables users to achieve additional power savings. the temperature sensor is enabled by default, and the partial-array self refresh can be programmed through the extended mode register. notes: 1. throughout the data sheet, various figures and text refer to dqs as ?dq.? the dq term is to be interpreted as any and all dq collectively, unless specifically stated oth- erwise. 2. complete functionality is described throughout the document, and any page or dia- gram may have been simplified to convey a topic and may not be inclusive of all requirements. 3. any specific requirement takes precedence over a general statement.
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 7 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram general description functional block diagrams figure 2: functional block diagram (16 meg x 16) 13 row- address mux control logic column- address counter/ latch standard mode register extended mode register 9 command decode a0?a12, ba0, ba1 cke ck# ck cs# we# cas# ras# 13 address register 15 i/o gating dm mask logic column decoder bank 0 memory array (8,192 x 256 x 32) bank 0 row- address latch and decoder 8,192 bank control logic 13 bank 1 bank 2 bank 3 13 8 2 2 refresh counter 16 16 16 2 input registers 2 2 2 2 rcvrs 2 32 32 4 32 ck out data dqs mas k data ck ck in drvrs mux dqs generator 16 16 16 16 16 32 dq0? dq15 ldqs, udqs 2 read latch write fifo and drivers 1 col 0 col 0 16,384 sense amplifiers ldm, udm ck 256 (x32)
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 8 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram general description figure 3: functional block diagram (8 meg x 32) notes: 1. jedec-standard x32 dq configuration shown. 13 ras# cas# row- address mux ck cs# we# ck# control logic column- address counter/ latch standard mode register extended mode register 9 command decode a0?a11, ba0, ba1 cke 12 address register 14 256 (x64) i/o gating dm mask logic bank 0 memory array (4,096 x 256 x 64) bank 0 row- address latch and decoder 8,192 bank control logic 12 bank 1 bank 2 bank 3 12 8 2 2 refresh counter 32 32 32 4 input registers 4 4 4 4 rcvrs 4 64 64 8 64 ck out data dqs mask data ck ck in drvrs mux dqs generator 32 32 32 32 32 64 dq0? dq31 dqs0 dqs1 dqs2 dqs3 4 read latch write fifo and drivers 1 col 0 col 0 dqm0 dqm1 dqm2 dqm3 ck column decoder 4,092 sense amplifiers
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 9 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram general description ballouts and ball descriptions figure 4: 60-ball vfbga ball assignments ? 8mm x 9mm (top view) notes: 1. d9 is a test pin that must be connected to v ss or v ss q in normal operation. 1 2 3 4 6 7 8 9 5 a b c d e f g h j k v ss q dq14 dq12 dq10 dq8 nc ck# a12 a8 a5 v ss v dd q v ss q v dd q v ss q v ss cke a9 a6 v ss dq15 dq13 dq11 dq9 udqs udm ck a11 a7 a4 v dd q dq1 dq3 dq5 dq7 nc we# cs# a10 /ap a2 dq0 dq2 dq4 dq6 ldqs ldm cas# ba0 a0 a3 v dd v ss q v dd q test 1 v dd q v dd ras# ba1 a1 v dd ball down
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 10 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram general description figure 5: 90-ball vfbga ball assignments ? 8mm x 13mm (top view) notes: 1. d9 is a test pin that must be connected to v ss or v ss q in normal operation. v ss q dq30 dq28 dq2 6 dq24 n c c k# a12 /dnu a8 a5 dq8 dq10 dq12 dq14 v ss q v ss v dd q v ss q v dd q v ss q v dd c ke a9 a 6 a4 v ss q v dd q v ss q v dd q v ss dq31 dq29 dq27 dq25 dq s 3 dm3 c k a11 a7 dm1 dq s 1 dq9 dq11 dq13 dq15 v dd q dq17 dq19 dq21 dq23 n c we# cs # a10 /ap a2 dq7 dq5 dq3 dq1 v dd q dq1 6 dq18 dq20 dq22 dq s 2 dm2 c a s # ba0 a0 dm0 dq s 0 dq 6 dq4 dq2 dq0 v dd v ss q v dd q te s t 1 v dd q v ss ra s # ba1 a1 a3 v dd q v ss q v dd q v ss q v dd 1 2 3 4 6 7 8 9 5 a b c d e f g h j k l m n p r ball down
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 11 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram general description table 3: 60-ball vfbga ball descriptions ball numbers symbol type description g2, g3 ck, ck# input clock : ck is the system clock input. ck and ck# are di fferential clock inputs. all address an d control input signal s are sampled on the crossing of the positive edge of ck and the negative edge of ck#. input and output data is referenced to the crossing of ck and ck# (both directions of the crossing). g1 cke input clock enable : cke high activates and cke low deactivates the internal clock sign als, input buffers, and ou tput drivers. taking cke low enables precharge power-down and self refresh operations (all banks idle) or active power-down (row active in any bank). cke is synchronous for all fu nctions except self refresh exit. all input buffers (except cke) are disabled du ring power-down and self refresh modes. h7 cs# input chip select : cs# enables (registered low) and disables (registered high) the command decoder. all co mmands are masked when cs# is registered high. cs# provides for ex ternal bank selection on systems with multiple banks. cs# is cons idered part of the command code. g9, g8, g7 ras#, cas#, we# input command inputs : ras#, cas#, and we# (along with cs#) define the command being entered. f2, f8 udm, ldm input input data mask : dm is an input mask si gnal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sample d on both edges of dqs. although dm balls are input-only, the dm load ing is designed to match that of dq and dqs balls. for the x16, ldm is dm for dq0?dq7, and udm is dm for dq8?dq15. h8, h9 ba0, ba1 input bank address inputs : ba0 and ba1 define to which bank an active, read, write, or prechar ge command is being applied. ba0 and ba1 also determine which mode regi ster (standard mode register or extended mode register) is load ed during a load mode register command. j8, j9, k7, k8, k2, k3, j1, j2, j3, h1, j7, h2, h3 a0?a12 input address inputs : provide the row address for active commands, and the column address a nd auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. during a prec harge command, a10 determines whether the precharge applies to one bank (a10 low, bank selected by ba0, ba1) or all banks (a10 high) . the address inputs also provide the op-code during a load mode register command. a8, b7, b8, c7, c8, d7, d8, e7, e3, d2, d3, c2, c3, b2, b3, a2 dq0?dq15 i/o data input/output : data bus for x16. e2, e8 udqs, ldqs i/o data strobe : output with read data, input with write data. dqs is edge-aligned with read data, center-aligned with write data. data strobe is used to capture data. a7, b1, c9, d1, e9 v dd q supply dq power supply. a3, b9, c1, e1 v ss q supply dq ground. a9, f9, k9 v dd supply power supply. a1, f1, k1 v ss supply ground. f3, f7 nc ? no connect : may be left unconnected. d9 test ? test pin that must be connected to vss or v ss q in normal operation.
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 12 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram general description table 4: 90-ball vfbga ball description ball numbers symbol type description g2, g3 ck, ck# input clock : ck is the system clock input. ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. input and output data is referenced to the crossing of ck and ck# (both directions of the crossing). g1 cke input clock enable : cke high activates and cke low deactivates the internal clock signals, input buffers, and output drivers. taking cke low enables precharge power-down and self refresh operations (all banks idle) or active power-down (row active in any bank). cke is synchronous for all functions except self refresh exit. all input buffers (except cke) are disabled du ring power-down and self refresh modes. h7 cs# input chip select : cs# enables the command de coder (registered low) and disables the command decoder (r egistered high). all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple ba nks. cs# is considered part of the command code. g9, g8, g7 ras#, cas#, we# input command inputs : ras#, cas#, and we# (alo ng with cs#) define the command being entered. k8, k2, f8, f2 dm0?dm3 input input data mask : dm is an input mask si gnal for write data. input data is masked when dm is sample d high along with that input data during a write access. dm is sampled on both edges of dqs. although dm balls are input-only, the dm load ing is designed to match that of dq and dqs balls. for the x32, dm0 is dm fo r dq0?dq7; dm1 is dm for dq8?dq15; dm2 is dm for dq16 ?dq23; and dm3 is dm for dq24? dq31. h8, h9 ba0, ba1 input bank address inputs : ba0 and ba1 define to which bank an active, read, write, or precharge command is being applied. ba0 and ba1 also determine which mode register (standard mode register or extended mode register) is load ed during a load mode register command. j8, j9, k7, k9, k1, k3, j1, j2, j3, h1, j7, h2 a0?a11 input address inputs : provide the row address for active commands, and the column address and auto precharge bit (a10) for read or write commands, to select one location out of the memory array in the respective bank. during a pr echarge command, a10 determines whether the precharge applies to on e bank (a10 low, bank selected by ba0, ba1) or all banks (a10 hi gh). the address in puts also provide the op-code during a load mode register command. h3 a12 /dnu input a12 is an address input for the lg reduced page-size option (see ?options? on page 1). leave as dnu for jedec-standard option. r8, p7, p8, n7, n8, m7, m8, l7, l3, m2, m3, n2, n3, p2, p3, r2, a8, b7, b8, c7, c8, d7, d8, e7, e3, d2, d3, c2, c3, b2, b3, a2 dq0?dq31 i/o data input/output : data bus for x32. l8, l2, e8, e2 dqs0?dqs3 i/o data strobe : output with read data, in put with write data. dqs is edge-aligned with read data, center-aligned with write data. data strobe is used to capture data. a7, b1, c9, d1, e9, l9, m1, n9, p1, r7 v dd q supply dq power supply.
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 13 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram general description a3, b9, c1, e1, l1, m9, n1, p9, r3 v ss q supply dq ground. a9, f1, r9 v dd supply power supply a1, f9, r1 v ss supply ground. f3, f7 nc ? no connect : may be left unconnected. d9 test ? test pin that must be connected to v ss or v ss q in normal operation. table 4: 90-ball vfbga ball description (continued) ball numbers symbol type description
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 14 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram functional description functional description the 256mb mobile ddr sdram is a high -speed cmos, dynamic random-access memory containing 268,435,456 bits. it is in ternally configured as a quad-bank dram. each of the 67,108,864-bit banks on the x16 is organized as 8,192 rows by 512 columns by 16 bits. each of the 67,108,864-bit banks on the x32 is organized as 4,096 rows by 512 columns by 32 bits for the stan dard addressing configuration. the 256mb mobile ddr sdram uses a double da ta rate architecture to achieve high- speed operation. the double data rate architecture is essentially a 2 n -prefetch architec- ture, with an interface designed to transfer two data words per clock cycle at the i/o balls. single read or write access for the 256mb mobile ddr sdram consists of a single 2 n -bit-wide, one-clock-cycle data transfer at the internal dram core and two corre- sponding n -bit-wide, one-half-clock-cycle da ta transfers at the i/o balls. read and write accesses to the mobile ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coin- cident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. the dll circuit that is typically used on standard ddr devices is not necessary on the mobile ddr sdram. it has been omitted to save power. prior to normal operation, the mobile ddr sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. initialization mobile ddr sdrams must be powered up and initialized in a predefined manner. operational procedures other than those sp ecified may result in undefined operation. if there is an interruption to the device power, the initialization routine must be followed to ensure proper functionality of the mobile ddr sdram. the clock stop feature is not available until the device has been properly initialized. to properly initialize the mobile ddr sdram, this sequence must be followed: 1. the core power (v dd ) and i/o power (v dd q) must be brought up simultaneously. it is recommended that v dd and v dd q be from the same power source, or v dd q must never exceed v dd . assert and hold cke high. 2. after power supply voltages are stable and th e cke has been driven high, it is safe to apply the clock. 3. after the clock is stable, a 200s (min) delay is required by the mobile ddr sdram prior to applying an executable command . during this time, a nop or deselect command must be issued on the command bus. 4. issue a precharge all command. 5. issue a nop or deselect command for at least t rp time. 6. issue an auto refresh command followed by a nop or deselect command for at least t rfc time. issue a second auto refresh command followed by a nop or deselect command for at least t rfc time. as part of the initialization sequence, two auto refresh commands must be issued.
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 15 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram register definition 7. using the load mode register command, load the standard mode register as desired. 8. issue a nop or deselect command for at least t mrd time. 9. using the load mode register command, load the extended mode register to the desired operating modes. note that the sequ ence in which the standard and extended mode registers are programmed is not critical. 10. issue nop or deselect commands for at least t mrd time. the mobile ddr sdram has been properly initialized and is ready to receive any valid command. register definition mode registers the mode registers are used to define the sp ecific mode of operation of the mobile ddr sdram. two mode registers are used to specify the operational characteristics of the device. standard mode register the standard mode register bit definition enables the selection of burst length, burst type, cas latency, and operating mode, as shown in figure 6 on page 16. reserved states should not be used, as this may result in setting the device into an unknown state or cause incompatibility with future versions of mobile ddr sdram. the standard mode register is programmed via the load mode register command (with ba0 = 0 and ba1 = 0) and will retain the stored informat ion until it is programmed again, the device goes into deep power-down mode, or the device loses power. reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. the mode register must be loaded when all banks are idle and no bursts are in progress, and the controller mu st wait before initiating the subsequent operation. violating any of these requiremen ts will result in unspecified operation. burst length read and write accesses to the mobile ddr sdram are burst oriented; the burst length is programmable. the burst length determines the maximum number of column loca- tions that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both se quential and interleaved burst types. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses fo r that burst take place within this block, meaning that the burst will wrap when a bo undary is reached. the block is uniquely selected by a1?a i when bl = 2, by a2?a i when bl = 4, and by a3?a i when bl = 8, where a i is the most significant column address bit for a given configuration. the remaining (least significant) address bits are used to specify the starti ng location within the block. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst may be programme d either to be sequential or interleaved via the standard mode register. the ordering of accesses within a burst is de termined by the burst length, the burst type, and the starting column address (see table 5 on page 17).
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 16 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram register definition cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first outp ut data. the latency can be set to two or three clocks, as shown in figure 7 on page 18. for cas latency three (cl = 3), if the read command is registered at clock edge n , then the data will nominally be available at ( n + 2 clocks + t ac ) . for cl = 2, if the read command is registered at clock edge n , then the data will be nominally be available at ( n + 1 clock + t ac). figure 6: standard mode register definition m3 0 1 c a s laten c y reserve d reserve d 2 3 reserve d reserve d reserve d reserve d burst len g th c a s laten c y bt 0 a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 s tan d ar d mo d e re g ister (mx) a dd ress bus m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m 6 0 0 0 0 1 1 1 1 operatin g mo d e a10 a12 a11 ba0 ba1 0 0 0 1 1 mo d e re g ister definition s tan d ar d mo d e re g ister reserve d exten d e d mo d e re g ister reserve d m14 0 1 0 1 m13 m12 m11 m10 m9 m8 m7 m 6 ?m0 operatin g mo d e 0 0 0 0 0 0 vali d normal operation ? ? ? ? ? ? all other states reserve d 10 11 12 13 14 9 7 6 5 4 8 3 2 1 0 burst type s equential interleave d m3 = 0 reserved 2 4 8 reserved reserved reserved reserved m3 = 1 reserved 2 4 8 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 17 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram register definition table 5: burst definition table burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 18 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram register definition figure 7: cas latency notes: 1. bl = 4 in the cases shown. 2. shown with nominal t ac and nominal t dqsq. c k c k# t 0 t1 t 2 t 2 n t 3 t 3 n t1n c k c k# t0 t1 t2 t2n t3 t3n c omman d dq dq s don ? t c are transitionin g d ata read nop nop nop d out n d out n+1 d out n+3 d out n+2 t a c c l = 2 1 n c lo c k c omman d dq dq s read nop nop nop d out n d out n+1 t a c 2 n c lo c k c l = 3
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 19 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram register definition operating mode the normal operating mode is selected by issuing a load mode register command with bits a7?a11 (x32) or a7?a12 (x16) each se t to zero and bits a0?a6 set to the desired values. all other combinations of values for a7?a11/a12 are reserved for future use and/or test modes. test modes and reserved states shou ld not be used, beca use unknown operation or incompatibility with future versions may result. extended mode register the extended mode register controls func tions specific to mobile sdram operation. these additional functions include drive strength, temperature-compensated self refresh, and partial-array self refresh. the extended mode register is programmed via the load mode register command (with ba0 = 0 and ba1 = 1) and will retain th e stored information until it is programmed again, the device goes into deep power-down mode, or the device loses power. temperature-compensated self refresh on this version of the mobile ddr sdram, a temperature sensor is implemented for automatic control of the self refresh oscill ator. programming the tcsr bits will have no effect on the device. the self refresh oscillator will continue to refresh at the factory-programmed optimal rate for the device temperature. partial-array self refresh for further power savings during self refresh, the partial-array self refresh (pasr) feature enables the controller to select the amount of memory that will be refreshed during self refresh. write and read commands can still occur du ring standard operation, but only the selected regions of the array will be refreshed during self refresh. data in regions that are not selected will be lost. output driver strength because the mobile ddr sdram is designed for use in smaller systems that are typically point-to-point connections, an option to control the drive strength of the output buffers is provided. drive strength should be select ed based on expected loading of the memory bus. there are four allowable settings for the output drivers: 25 , 55 , 80 , and 100 internal impedance. table 6: partial-array self refresh options memory bank full array banks 0, 1, 2, and 3 half array banks 0 and 1 quarter array bank 0 eighth array bank 0 with row address msb = 0 sixteenth array bank 0 with row address msb = 0 and msb - 1 = 0
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 20 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram register definition figure 8: extended mode register notes: 1. on-die temperature sensor is used in plac e of tcsr. setting these bits will have no effect. stopping the external clock one method of controlling the power efficiency in applications is to throttle the clock that controls the ddr sdram. control the clock in two ways: ? change the clock frequency. ? stop the clock. the mobile ddr sdram enables the clock to change frequency during operation only if all the timing parameters are met and all refresh requirements are satisfied. the clock can be stopped if no dram operations are in progress that would be affected by this change. any dram operation alread y in process must be completed before entering clock stop mode; this includes the following timings: t rcd, t rp, t rfc, t mrd, t wr, and all data-out for read bursts. for example, if a write or a read is in progress, the entire data burst must be complete prior to stopping the clock. for reads, a bu rst completion is defined when the read postamble is satisfied. for writes, a burst completion is defined when the write post- amble and t wr or t wtr are satisfied. exten d e d mo d e re g ister a dd ress bus 97 6 54 3 821 pa s r t cs r 1 d s s et to ? 0 ? 0 e12 a11 e11 a10 e10 a9 e9 a8 e8 a7 e7 a 6 e 6 a5 e5 a4 e4 a3 e3 a2 e2 a1 e1 a0 e0 10 11 12 e2 0 0 0 0 1 1 1 1 e1 0 0 1 1 0 0 1 1 e0 0 1 0 1 0 1 0 1 partial-array s elf refresh c overa g e full array half array quarter array reserve d reserve d one-ei g hth array one-sixteenth array reserve d e 6 0 0 1 1 e5 0 1 0 1 driver s tren g th full-stren g th d river half-stren g th d river quarter-stren g th d river one-ei g hth-stren g th d rive r ba0 a12 e13 ba1 e14 1 13 14 0 0 1 1 mo d e re g ister definition s tan d ar d mo d e re g ister reserve d exten d e d mo d e re g ister reserve d e14 0 1 0 1 e13 0 e11 0 ? e12 0 ? e10 0 ? e9 0 ? e8 0 ? e7 0 ? vali d ? normal operation all other states reserve d e 6 ?e0 operatin g mo d e
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 21 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram register definition cke must be held high with ck = low and ck# = high for the full duration of the clock stop mode. one clock cycle and at least one nop or deselect is required after the clock is restarted before a valid command can be issued. figure 9 on page 21 illus- trates the clock stop mode. figure 9: clock stop mode notes: 1. prior to ta1, the device is in cloc k stop mode. to exit, at least one nop is re q uired before any valid command is issued. 2. any valid command is allowed; device is not in clock stop mode. exit c lo c k stop mo d e c ke c k c k# c omman d ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop nop t b 3 ta2 ta1 t b 4 don ? t c are a dd ress ( ) ( ) ( ) ( ) dq, dq s (hi g h-z) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) enter c lo c k stop mo d e ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) all dram a c tivities must b e c omplete c md 2 v ali d c md 2 v ali d nop 1 ( ) ( ) ( ) ( )
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 22 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram commands commands tables 7 and 8 provide a quick reference of available commands. this is followed by a description of each command. three additi onal truth tables provide cke commands and current/next state information (see table 9 on page 51, table 10 on page 52, and table 11 on page 54). notes: 1. cke is high for all commands shown except self refresh and deep power-down. 2. all states and se q uences not shown are reserved and/or illegal. 3. deselect and nop are functionally interchangeable. 4. ba0?ba1 provide bank address and a0?a12/a13 provide row address. 5. ba0?ba1 provide bank address; a0?a8 provide column address; a10 hi gh enables the auto precharge feature (nonpersistent); a10 lo w disables the auto precharge feature. 6. applies only to read bursts with auto precharge disabl ed; this command is undefined (and should not be used) for read bursts with au to precharge enabled and for write bursts. 7. this command is a burst terminate if cke is high and deep power-down if cke is low. 8. a10 low: ba0?ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0 ? ba1 are ?don?t care.? 9. this command is auto refresh if cke is high, self refresh if cke is low. 10. internal refresh counter controls row addressi ng; all self refresh inpu ts and i/os are ?don?t care? except for cke. 11. ba0?ba1 either select the standard mode register or the exte nded mode register (ba0 = 0, ba1 = 0 select the standard mode re gister; ba0 = 0, ba1 = 1 select extended mode register; other combinations of ba0?ba1 are reserved). a0?a12/a13 pr ovide the op-code to be written to the selected mode register. notes: 1. used to mask write data; provided coincident with the corresponding data. 2. all states and se q uences not shown are reserved and illegal. table 7: truth table ? commands notes 1 and 2 appl y to all commands name (function) cs# ras# cas# we# address notes deselect (nop) hxx x x 3 no operation (nop) lhhh x 3 active (select bank and activate row) l l h h bank/row 4 read (select bank and colu mn, and start read burst) l h l h bank/column 5 write (select bank and column, and start write burst) l h l l bank/column 5 burst terminate or deep power-down (enter deep power-down mode) lhh l x 6, 7 precharge (deactivate row in bank or banks) l l h l code 8 auto refresh (refresh all or single bank) or self refresh (enter self refresh mode) lllh x 9, 10 load mode register (standard or extended mode registers) lll l op-code 11 table 8: truth table ? dm operation name (function) dm dq notes write enable l valid 1, 2 write inhibit hx1, 2
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 23 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram commands deselect the deselect function (cs# high) prevents new commands from being executed by the mobile ddr sdram. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to instruct the s elected mobile ddr sdram to perform a nop (cs# is low with ras#, cas#, and we# high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode registers are loaded via inputs ba0?ba1 and a0?a12. see mode register descriptions in ?register definition? on page 15. the load mode register command can only be issued when all bank s are idle, and a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0 and ba1 inputs selects the bank, and the address provided on inputs a0?a12 selects the row. this row remains active (or open) for accesses until a precha rge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a i (where i = the most significant column address bit for each configuration) selects the starting column location. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. write the write command is used to initiate a burst write access to an active row. the value on the ba0?ba1 inputs selects the bank, and the address provided on inputs a0?a i (where i = the most significant column address bit for each configuration) selects the starting column location. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is no t selected, the row will remain open for subse- quent accesses. input data appearing on the dq is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location.
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 24 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram commands precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. the exception is the case of concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. inpu t a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? after a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank . a precharge command will be treated as a nop if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. burst terminate the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most recently registered read command prior to the burst terminate command will be truncated, as described in ?operations? on page 26. the open page from which the read bu rst was terminated remains open. auto refresh the auto refresh command is nonpersistent and must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a ?don?t care? during an auto refresh command. the 256mb mobile ddr sdram requires auto refresh cycles at an average interval of 7.8125s (max). to enable improved efficiency in scheduling and switching between tasks, some flexi- bility in the absolute refr esh interval is provided. although not a jedec requirement, cke must be active (high) during the auto refresh period to provide for future functionality fe atures. the auto refresh period begins when the auto refresh command is registered, and it ends t rfc later. self refresh the self refresh command can be used to retain data in the mobile ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the mobile ddr sdram retains data without external clocking. the self refresh command is initiated like an auto refres h command, except that cke is disabled (low). all command and address input sign als except cke are ?don?t care? during self refresh. for details on entering and exiting self refresh mode, see figure 44 on page 72. during self refresh, the device is refreshed as identified in the extended mode register (see pasr setting). auto precharge auto precharge is a feature that performs the same individual-bank precharge func- tion described above, without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon co mpletion of the read or write burst.
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 25 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram commands auto precharge is nonpersistent in that it is either enabled or disabled for each indi- vidual read or write command. this device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. auto precharge ensures that the precharge is in itiated at the earliest valid stage within a burst. this earliest valid stage is determined as if an explicit precharge command were issued at the earliest possible time, without violating t ras (min), as described for each burst type in ?operations? on page 26. the user must not issue another command to the same bank until the precharge time ( t rp) is completed. deep power-down deep power-down is an operating mode used to achieve maximum power reduction by eliminating the power draw of the memory array. data will not be retained when the device enters deep power-down mode. figure 10: mobile dram state diagram power on power applie d dpd s x ref s x mr s refa ref s dpd s a c t c kel c kel c keh c keh pre pre c har g e all b anks mr s emr s deep power- d own s elf refresh i d le all b anks pre c har g e d row a c tive burst stop read read a automati c sequen c e c omman d sequen c e write write write write a write a pre c har g e preall a c tive power- d own pre c har g e power- d own auto refresh pre write a read a read a pre pre read a read read read b s t
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 26 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations operations bank/row activation before any read or write commands can be issued to a bank within the mobile ddr sdram, a row in that bank must be ?opene d.? this is accomplished via the active command, which selects both the bank and the row to be activated, as shown in figure 11. after a row is opened with an active command, a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 133 mhz clock (7.5ns period) results in 2.7 clocks rounded to 3. this is reflected in figure 12 on page 27, which covers any case where 2 < t rcd (min)/ t ck 3. (figure 12 also shows the same case for t rrd; the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active comma nds to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to different banks is defined by t rrd. figure 11: activating a specific row in a specific bank notes: 1. ra = row address 2. ba = bank address cs # we# c a s # ra s # c ke a0?a12 ra hi g h ba0, ba1 ba c k c k#
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 27 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 12: example: meeting t rcd ( t rrd) min when 2 < t rcd ( t rrd) min reads read burst operations are initiated with a read command, as shown in figure 13 on page 28. the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out elem ent from the starting column address will be available following the cas latency after the read command. each subsequent data- out element will be valid nominally at the next positive or negative clock edge (for example, at the next crossing of ck and ck#). figure 14 on page 29 shows general timing for different cas latency settings. dqs is driven by the mobile ddr sdram along with output data. the initial low state on dqs is known as the read preamble; the low state coincident with the last data-out el ement is known as the read postamble. upon completion of a burst, assuming no ot her commands have been initiated, the dq will go high-z. a detailed explanation of t dqsq (valid data-out skew), t qh (data-out window hold), and the valid data window is depicted in figure 37 on page 66. a detailed explanation of t dqsck (dqs transition skew to ck) and t ac (data-out transition skew to ck) is depicted in figure 39 on page 68. data from any read burst may be concatenat ed with or truncated with data from a subsequent read command. in either case, a continuous flow of data can be main- tained. the first data element from the new burst either follows the last element of a completed burst or the last desired data elem ent of a longer burst that is being trun- cated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). this is shown in figure 15 on page 30. a read command can be initiated on any clock cycle following a previous read command. nonconsecutive read data is illustrated in figure 16 on page 31. full-speed random read accesses within a page (or pages) can be performed, as shown in figure 17 on page 32. c omman d ba0, ba1 a c t a c t nop t rrd t r c d c k c k# bank x bank y a0?a12 row row nop rd/wr nop bank y c ol nop t0 t1 t2 t3 t4 t5 t 6 t7 don ? t c are nop
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 28 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 13: read command notes: 1. ca = column address 2. ba = bank address 3. en ap = enable auto precharge 4. dis ap = disable auto precharge 5. x16 dq configuration example cs # we# c a s # ra s # c ke c a a0?a8 a10 ba0,1 hi g h en ap di s ap ba a9, a11, a12 c k c k# don ? t c are
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 29 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 14: read burst notes: 1. d out n = data-out from column n . 2. bl = 4. 3. shown with nominal t ac, t dqsck, and t dqsq. c k c k# c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t0 t1 t2 t3 t2n t3n t4 t5 t1n c omman d read nop nop nop nop nop a dd ress bank a, c ol n don ? t c are transitionin g d ata dq dq s c l = 2 c l = 3 d out n+1 d out n+3 d out n+2 c ommman d read nop nop nop nop nop a dd ress bank a, c ol n dq dq s d out n+1 d out n+3 d out n+2 d out n d out n
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 30 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 15: consecutive read bursts notes: 1. d out n (or b ) = data-out from column n (or column b ). 2. bl = 4 or 8 (if 4, the bursts are concatenated; if 8, the se cond burst interrupts the first). 3. shown with nominal t ac, t dqsck, and t dqsq. 4. example applies only when read comm ands are issued to the same device. c k c k# c k c k# t0 t1 t2 t3 t2n t3n t4 t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n t5 t4n t5n c omman d read nop read nop nop nop a dd ress bank, c ol n bank, c ol b c omman d nop read nop nop nop a dd ress bank, c ol b don ? t c are transitionin g d ata dq dq s c l = 2 c l = 3 d out n d out n+1 d out n+3 d out n+2 d out b d out b+2 d out b+1 d out b + 3 dq dq s d out n d out n+1 d out n+3 d out n+2 d out b d out b+1 read bank, c ol n
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 31 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 16: nonconsecutive read bursts notes: 1. d out n (or b ) = data-out from column n (or column b ). 2. bl = 4 or 8 (if burst is 8, th e second burst interrupts the first). 3. shown with nominal t ac, t dqsck, and t dqsq. 4. example applies when read co mmands are issued to differen t devices or nonconsecutive reads. c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n t 6 c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n t 6 c omman d read nop nop nop nop nop a dd ress bank, c ol n read bank, c ol b don ? t c are transitionin g d ata dq dq s c l = 2 d out n d out n+1 d out n+3 d out n+2 d out b d out b+1 d out b+2 c l = 2 c l = 3 c l = 3 c omman d read nop nop nop nop nop a dd ress bank, c ol n read bank, c ol b dq dq s d out n d out n+1 d out n+3 d out n+2 d out b
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 32 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 17: random read accesses notes: 1. d out n (or x , b , g ) = data-out from column n (column x , column b, column g ). 2. bl = 2, 4, or 8 (if 4 or 8, the following burst inte rrupts the previous). 3. reads are to an active row in any bank. 4. shown with nominal t ac, t dqsck, and t dqsq. c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n c omman d read read read nop nop a dd ress bank, c ol n bank, c ol x bank, c ol b bank, c ol x bank, c ol b read bank, c ol g c omman d a dd ress read read nop nop read bank, c ol g don ? t c are transitionin g d ata dq dq s c l = 2 c l = 3 d out n+1 d out x+1 d out x d out b d out g d out b+1 d out g +1 dq dq s d out n d out n+1 d out x+1 d out x d out b d out b+1 d out n read bank, c ol n
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 33 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations truncated reads data from any non-auto precharge read burst may be truncated with a burst termi- nate command, as shown in figure 18. the burst terminate latency is equal to the read (cas) latency; for example, the burst terminate command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). data from any non-auto precharge read burs t must be completed or truncated before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used, as shown in figure 18. the t dqss (min) case is shown; the t dqss (max) case has a longer bus idle time. ( t dqss [min] and t dqss [max] are defined in the section on writes.) a read burst may be followed by, or tr uncated with, a precharge command to the same bank provided that auto precharge was not activated. the precharge command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the n -prefetch architecture). this is shown in figure 20 on page 35. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note: part of the row precharge time is hidden du ring the access of the last data elements. figure 18: terminating a read burst notes: 1. d out n = data-out from column n . 2. bl = 4 or 8. 3. shown with nominal t ac, t dqsck, and t dqsq. 4. bst = burst terminate comm and; page remains open. c k c k# t0 t1 t2 t3 t2n t4 t5 t1n c omman d read b s t 4 nop nop nop nop a dd ress bank a , c ol n don ? t c are transitionin g d ata dq dq s c l = 2 c l = 3 d out n n+1 d out c k c k# t0 t1 t2 t3 t2n t4 t5 t3n c omman d read b s t 4 nop nop nop nop a dd ress bank a , c ol n dq dq s n+1 d out d out n
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 34 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations 5. cke = high. figure 19: read-to-write notes: 1. d out n = data-out from column n . 2. d in b = data-in from column b . 3. bl = 4 in the cases shown (app lies for bursts of 8 as well; if bl = 2, the bst command shown can be a nop). 4. shown with nominal t ac, t dqsck, and t dqsq. 5. bst = burst terminate comm and; page remains open. 6. cke = high. ck# t 0 t1 t 2 t 3 t 2 n t 3 n t4 t5 t1n t4n t5n ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n ck don?t care transitioning data command read bst 5 nop nop nop address bank, col n write bank, col b dm dq dqs d out n d out n+1 d in b+1 d in b d in b+2 d in b+3 command bst 5 nop nop address write bank, col b dm dq dqs d out n d out n+1 d in b+1 d in b t dqss (nom) t dqss (nom) read bank, col n nop cl = 2 cl = 3
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 35 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 20: read-to-precharge notes: 1. d out n = data-out from column n . 2. bl = 4 or an interrupted burst of 8. 3. shown with nominal t ac, t dqsck, and t dqsq. 4. read-to-precharge e q uals 2 clock cycles, which allows 2 data pairs of data-out. 5. a read command with auto pr echarge enabled, provided t ras (min) is met, would cause a precharge to be performed at x number of clock cycles after the read command, where x = bl/2. 6. pre = precharge command; act = active command. ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n command 5 read nop pre nop nop act address bank a , col n dq dqs cl = 2 d out n d out n+1 d out n+3 d out n+2 t rp cl = 3 t rp read nop pre nop nop act bank a , col n command 5 address bank a , ( a or all ) bank a , row dq dqs d out n d out n+1 d out n+3 d out n+2 don?t care transitioning data bank a , ( a or all ) bank a , row
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 36 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations writes write bursts are initiated with a write command, as shown in figure 21 on page 37. the starting column and bank addresses ar e provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at th e completion of the burst. for the write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered on the first rising edge of dqs following the write command, and subsequent data elements will be registered on successive edges of dqs. the low state on dqs between the write command and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time between the write command and th e first corresponding rising edge of dqs ( t dqss) is specified with a relatively wide range (from 75 percent to 125 percent of one clock cycle). all the write diagrams show the nominal case, and where the two extreme cases (for example, t dqss [min] and t dqss [max]) might not be intuitive, they have also been included. figure 22 on page 38 shows the nominal case and the extremes of t dqss for a burst of 4. upon completion of a burst, assuming no other commands have been initiated, the dq will remain high-z, an d any additional input data will be ignored. data for any write burst may be concatenat ed with or truncated with a subsequent write command. in either case, a continuous flow of input data can be maintained. the new write command can be issued on any positive edge of clock following the previous write command. the first data elem ent from the new burst is applied either after the last element of a completed burst or the last desired data element of a longer burst that is being truncated. the new write command should be issued x cycles after the first write command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). figure 23 on page 39 shows concatenated burs ts of 4. an example of nonconsecutive writes is shown in figure 24 on page 39. full-speed random write accesses within a page or pages can be performed, as shown in figure 25 on page 40. data for any write burst may be followed by a subsequent read command. to follow a write without truncating the write burst, t wtr should be met, as shown in figure 26 on page 41. data for any write burst may be truncated by a subsequent read command, as shown in figure 27 on page 42. note that only the data-in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent data-in should be masked with dm, as shown in figure 28 on page 43. data for any write burst may be followed by a subsequent precharge command. to follow a write without truncating the write burst, t wr should be met, as shown in figure 29 on page 44. at least one clock cycle is required during t wr time when in auto- precharge mode. data for any write burst may be truncated by a subsequent precharge command, as shown in figure 30 on page 45 and figure 31 on page 46. note that only the data-in pairs that are registered prior to the t wr period are written to the internal array, and any subsequent data-in should be masked with dm, as shown in figures 30 and 31. after the precharge command, a subsequent command to the same bank cannot be issued until t rp is met.
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 37 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 21: write command notes: 1. ca = column address. 2. ba = bank address. 3. en ap = enable auto precharge. 4. dis ap = disable auto precharge. cs # we# c a s # ra s # c ke c a a10 ba0, ba1 hi g h en ap di s ap ba c k c k# don ? t c are a0?a9 a11, a12
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 38 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 22: write burst notes: 1. d in b = data-in for column b . 2. an uninterrupted burst of 4 is shown. 3. a10 is low with the write comm and (auto precharge is disabled). dq s t d qss (max) t d qss (nom) t d qss (min) t dq ss t dq ss t dq ss dm dq c k c k# c omman d write nop nop a dd ress bank a , c ol b nop t 0 t1 t 2 t 3 t 2 n dq s dm dq dq s dm dq d in b don ? t c are transitionin g d ata d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 39 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 23: consecutive write-to-write notes: 1. d in b ( n ) = data-in for column b ( n ). 2. an uninterrupted burst of 4 is shown. 3. each write command may be to any bank. figure 24: nonconsecutive write-to-write notes: 1. d in b (n) = data-in for column b (n). 2. an uninterrupted burst of 4 is shown. 3. each write command may be to any bank. c k c k# c omman d write nop write nop nop a dd ress bank, c ol b nop bank, c ol n t0 t1 t2 t3 t2n t4 t5 t4n t3n t1n dq dq s dm don ? t c are transitionin g d ata t dq ss t d qss (nom) d in n d in n+1 d in n+2 d in n+3 d in b d in b+1 d in b+2 d in b+3 c k c k# c omman d write nop nop nop nop a dd ress bank, c ol b write bank, c ol n t 0 t1 t 2 t 3 t 2 n t4 t5 t4n t1n t5n dq dq s dm t d qss (nom) t dq ss don ? t c are transitionin g d ata d in b d in b+1 d in b+2 d in b+3 d in n d in n+1 d in n+2 d in n+3
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 40 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 25: random write cycles notes: 1. d in b (or x, n, a, g ) = data-in for column b (or x, n, a, g ). 2. b' (or x', n', a', g' ) = the next data-in following d in b (x, n, a, g) , according to the pro- grammed burst order. 3. programmed bl = 2, 4, or 8 in cases shown. 4. each write command may be to any bank. t dq ss (nom) c k c k# c omman d write write write write nop a dd ress bank, c ol b bank, c ol x bank, c ol n bank, c ol g write bank, c ol a t0 t1 t2 t3 t2n t4 t5 t4n t1n t3n t5n dq dq s dm d in b d in b ' d in x d in x ' d in n d in n ' d in a d in a ' d in g d in g' don ? t c are transitionin g d ata
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 41 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 26: write-to-read ? uninterrupting notes: 1. d in b = data-in for column b ; d out n = data-out for column n . 2. an uninterrupted burst of 4 is shown. 3. t wtr is referenced from the first positive ck edge after the last data-in pair. 4. the read and write commands are to the same bank. however, the read and write commands can be directed to di fferent banks in which case t wtr is not re q uired, and the read command could be applied earlier. 5. a10 is low with the write comm and (auto precharge is disabled). t d qss (nom) c k c k# c omman d write nop nop read nop nop a dd ress bank a , c ol b bank a , c ol n nop t0 t1 t2 t3 t2n t4 t5 t1n t 6 t 6 n t wtr c l = 2 dq dq s dm d out n t dq ss t d qss (min) c l = 2 dq dq s dm t dq ss t d qss (max) c l = 2 dq dq s dm t dq ss don ? t c are transitionin g d ata d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 d out n+1 d out n d out n+1 d out n d out n+1 t5n
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 42 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 27: write-to-read ? interrupting notes: 1. d in b = data-in for column b; d out n = data-out for column n . 2. an interrupted burst of 4 is show n; two data elements are written. 3. t wtr is referenced from the first positive ck edge after the last data-in pair. 4. a10 is low with the write comm and (auto precharge is disabled). 5. dqs is re q uired at t2 and t2n (nominal case) to register dm. 6. if the burst of 8 was used, dm and dqs would be re q uired at t3 and t3n because the read command would not mask th ese two data elements. t d qss (nom) c k c k# c omman d write nop nop nop nop nop a dd ress bank a , c ol b bank a , c ol n read t0 t1 t2 t3 t2n t4 t5 t5n t1n t 6 t 6 n t wtr c l = 3 dq dq s dm d in b d out n t d qss (min) c l = 3 dq dq s dm t d qss (max) c l = 3 dq dq s dm don ? t c are transitionin g d ata t dq ss t dq ss t dq ss d in b+1 d in b+1 d in b d in b+1 d in b d out n+1 d out n d out n+1 d out n d out n+1
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 43 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 28: write-to-read ? odd number of data, interrupting notes: 1. d in b = data-in for column b; d out n = data-out for column n . 2. an interrupted burst of 4 is shown; one da ta element is written, and three are masked. 3. t wtr is referenced from the first positive ck edge after the last data-in. 4. a10 is low with the write comm and (auto precharge is disabled). 5. dqs is re q uired at t2 and t2n (nominal case) to register dm. 6. if the burst of 8 was used, dm and dqs would be re q uired at t3 and t3n because the read command would not mask th ese two data elements. t dq ss (nom) c k c k# c omman d write nop nop nop nop nop a dd ress bank a, c ol b bank a, c ol n read t0 t1 t2 t3 t2n t4 t5 t5n t1n t 6 t 6 n t wtr c l = 3 dq dq s dm d in b d out n t dq ss (min) c l = 3 dq dq s dm t dq ss (max) c l = 3 dq dq s dm don ? t c are transitionin g d ata t dq ss d in b d in b d out n+1 d out n d out n+1 d out n d out n+1 t dq ss t dq ss
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 44 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 29: write-to-precharge ? uninterrupting notes: 1. d in b = data-in for column b . 2. an uninterrupted burst of 4 is shown. 3. t wr is referenced from th e first positive ck edge af ter the last data-in pair. 4. the precharge and write commands are to the same bank. however, the precharge and write commands may be to different banks in which case t wr is not re q uired, and the precharge command coul d be applied earlier. 5. a10 is low with the write comm and (auto precharge is disabled). 6. pre = precharge command. t d qss (nom) c k c k# c omman d write nop nop nop nop a dd ress bank a , c ol b bank ( a or all) nop t0 t1 t2 t3 t2n t4 t5 t1n t 6 dq dq s dm t dq ss t d qss (min) dq dq s dm t dq ss t d qss (max) dq dq s dm t dq ss don ? t c are transitionin g d ata d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 t wr pre 6
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 45 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 30: write-to-precharge ? interrupting notes: 1. d in b = data-in for column b . 2. an interrupted burst of 8 is show n; two data elements are written. 3. t wr is referenced from th e first positive ck edge af ter the last data-in pair. 4. a10 is low with the write comm and (auto precharge is disabled). 5. pre = precharge command. 6. dqs is re q uired at t4 and t4n (nominal case) to register dm. 7. if a burst of 4 is used, dqs and dm are not re q uired at t3, t3n, t4, and t4n. t dq ss (nom) c k c k# c omman d write nop nop nop nop a dd ress bank a, c ol b bank (a or all) nop t0 t1 t2 t3 t2n t4 t5 t1n t6 dq dq s dm t dq ss t dq ss (min) dq dq s dm t dq ss t dq ss (max) dq dq s dm t dq ss don ? t c are transitionin g d ata t wr pre 5 t4n t3n d in b d in b + 1 d in b d in b + 1 d in b d in b + 1
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 46 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 31: write-to-precharge ? odd number of data, interrupting notes: 1. d in b = data-in for column b . 2. an interrupted burst of 8 is shown. 3. t wr is referenced from th e first positive ck edge af ter the last data-in pair. 4. a10 is low with the write comm and (auto precharge is disabled). 5. pre = precharge command. 6. dqs is re q uired at t4 and t4n to register dm. 7. if the burst of 4 is used, dqs and dm are not re q uired at t3, t3n, t4, and t4n. t dq ss (nom) c k c k# c omman d write nop nop nop nop a dd ress bank a, c ol b bank (a or all) nop t0 t1 t2 t3 t2n t4 t5 t1n t 6 dq dq s dm t dq ss t dq ss (min) dq dq s dm t dq ss t dq ss (max) dq dq s dm t dq ss don ? t c are transitionin g d ata d in b d in b d in b t wr 2 pre 5 t4n t3n
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 47 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations precharge the precharge command (figure 32) is used to deactivate the open row in a partic- ular bank or the open row in all banks. th e bank(s) will be available for a subsequent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged. in the case where only one bank is to be precharged (a10 = low) , inputs ba0?ba1 select the bank. when all banks are to be precharged (a10 = high), inputs ba0?ba1 are treated as a ?don?t care.? after a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. figure 32: precharge command notes: 1. ba = bank address. 2. a10 = 1 high, all banks to be precharged, ba1, ba0 are ?don?t care.? 3. a10 = 0 low, only bank selected by ba1 and ba0 will be precharged. 4. i = the most significant column ad dress bit for each configuration. cs # we# c a s # ra s # c ke a10 ba0, ba1 hi g h all s in g le ba c k c k# don ? t c are a0?a9, a11?a i
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 48 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations power-down power-down (figure 42 on page 70) is entered when cke is registered low. if power- down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down de activates all input and output buffers, including ck and ck# and excluding cke. exiting power-down requires the device to be at the same voltage as when it entered power-down and received a stable clock. note: the power-down duration is limited by the refresh requirements of the device. while in power-down, cke low must be maintained at the inputs of the mobile ddr sdram, while all other input si gnals are ?don?t care.? the power-down state is exited when cke is registered high (in conjunct ion with a nop or deselect command). a nop or deselect command must be maintained on the command bus until t xp is satisfied. figure 33: power-down command (in active or precharge modes) cs # ra s #, c a s #, we# c ke ba0,1 c k c k# don ? t c are a0?a12 ra s #, c a s #, we# cs # ba0?ba1 or
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 49 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations deep power-down (dpd) deep power-down is an operating mode used to achieve maximum power reduction by eliminating the power of the memory array. da ta will not be retained when the device enters deep power-down mode. before entering dpd mode, the dram must be in all banks idle state with no activity on the data bus ( t rp time must be met). this mode is entered by holding cs# and we# low with ras# and cas# high at the rising edge of the clock, while ck e is low. cke must be held low to maintain dpd mode. the clock must be stable prior to exiting dpd mode. this mode is exited by asserting cke high with either a nop or deselect command present on the command bus. upon exit from dpd mode, 200s of valid clocks either with a nop or deselect command present on the command bus are required, and a precharge all command and a full dram initialization sequence are required. figure 34: deep power-down command cs# we# cas# ras# cke a0?a12 ba0, ba1 don?t care
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 50 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations figure 35: deep power-down notes: 1. clock must be stable prior to cke going high. 2. dpd = deep power-down command. 3. upon exit from deep power-down mode , a precharge all comma nd must be issued, followed by the initialization se q uence (see page 14). t i s all b anks i d le with no a c tivity on the d ata b us exit d eep power- d own mo d e enter d eep power- d own mo d e c ke c k c k# cd omman d dpd 2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop nop vali d 3 t0 t1 t2 ta0 1 ta1 ta2 nop don ? t c are t c ke ta3 t = 200s
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 51 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations notes: 1. cke n is the logic state of cke at clock edge n ; cke n - 1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n. 3. command n is the command registered at clock edge n ; and action n is a result of com- mand n . 4. all states and se q uences not shown are illegal or reserved. 5. t cke pertains. 6. deselect or nop commands should be issued on any clock edges occurring during the t xp period. 7. the clock must toggle at least one time during the t xp period. 8. deselect or nop commands should be issued on any clock edges occurring du ring the t xsr period. 9. the clock must toggle at least one time during the t xsr period. 10. 200s of valid clocks and nop (or deselect) commands are re q uired before any other valid command is allowed. 11. upon exit from deep power-down mode and after the 200s, a precharge all command is re q uired, followed by the standard initialization se q uence. table 9: truth table ? cke notes 1?5 apply to all commands in this table cke n - 1 cke n current state command n action n notes ll active power-down x maintain active power-down ll deep power-down x maintain deep power-down ll (precharge) power-down x maintain (prech arge) power-down ll self refresh x maintain self refresh lh active power-down deselect or nop exit active power-down 6, 7 lh deep power-down deselect or nop exit deep power-down 10, 11 lh (precharge) power-down deselect or nop exit (precharge) power-down 6, 7 lh self refresh deselect or nop exit self refresh 8, 9 hl bank(s) active deselect or nop active power-down entry hl all banks idle burst terminate deep power-down entry hl all banks idle deselect or nop (precharge) powe r-down entry hl all banks idle auto refresh self refresh entry h h see table 11 on page 54
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 52 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations notes: 1. this table applies when cke n - 1 was high and cke n is high and after t xsr has been met (if the previous state was self refresh), after t xp has been met (if the previous state was power-down), or 200s if the previous state was dpd. 2. this table is bank-specific, except where note d (for example, the current state is for a spe- cific bank and the commands shown are those allo wed to be issued to that bank when in that state). exceptions are discussed in the notes below. 3. current state definitions: 4. the following states must not be interru pted by a command issued to the same bank. command inhibit or nop commands, or allowable commands to the other bank should be issued on any cloc k edge occurring during these states. allowable commands to any other bank are determined by that bank?s current state. table 10: truth table ? current state bank n ? command to bank n notes 1?6 apply to all states listed in this table; notes appear below and on next page current state cs# ras# cas# we# command (action) notes any hxxx deselect (nop/continu e previous operation) lhhh no operation (nop/conti nue previous operation) idle llhh active (select and activate row) lllh auto refresh 7 llll load mode register 7 row active lhlh read (select column and start read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (deactivate row in bank or banks) 8 read (auto precharge disabled) lhlh read (select column and start new read burst) 10 lhl l write (select column and start write burst) 10, 12 llhl precharge (truncate read burst, start precharge) 8 lhhl burst terminate 9 write (auto precharge disabled) lhlh read (select column and start read burst) 10, 11 lhl l write (select column an d start new write burst) 10 llhl precharge (truncate write burst, start precharge) 8, 11 idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regist er accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. precharging: starts with registration of a precharge command and ends when t rp is met. when t rp is met, the bank will be in the idle state. row activating: starts with registration of an active comma nd and ends when t rcd is met. when t rcd is met, the bank will be in the row active state. read with auto precharge enabled: starts with registration of a re ad command with auto precharge enabled and ends when t rp has been met. when t rp is met, the bank will be in the idle state. write with auto precharge enabled: starts with registration of a wri te command with auto precharge enabled and ends when t rp has been met. when t rp is met, the bank will be in the idle state.
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 53 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations 5. : the following states must not be interr upted by any executable command; dese- lect or nop commands must be applied on each positive clock edge during these states. 6. all states and se q uences not shown are illegal or reserved. 7. not bank-specific; re q uires that all banks be idle, and bursts not be in progress. 8. may or may not be bank-specifi c; if multiple banks are to be precharged, each must have an open row. 9. not bank-specific; burst terminate affects the most recent read burst, regardless of bank. 10. reads or writes listed in the command (act ion) column include reads or writes with auto precharge enabled and reads or wr ites with auto precharge disabled. 11. re q uires appropriate dm masking. 12. a write command may be applied after the co mpletion of the read burst; otherwise, a burst terminate must be used to end the read burst prior to asserting a write com- mand. refreshing starts with registration of an auto refresh command and ends when t rfc is met. when t rfc is met, the mobile ddr sdram will be in the all banks idle state. accessing mode register starts with registration of a load mode register command and ends when t mrd has been met. when t mrd is met, the mobile ddr sdram will be in the all banks idle state. precharging all: starts with registration of a prec harge all command and ends when t rp is met. when t rp is met, all banks will be in the idle state.
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 54 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations notes: 1. this table applies when cke n - 1 was high and cke n is high and after t xsr has been met (if the previous state was self refresh) or after t xp has been met (if the previous state was power-down) or 200s if the prev ious state was deep power-down). 2. this table describes alternate bank operatio n, except where noted (for example, the cur- rent state is for bank n and the commands sh own are those allowed to be issued to bank m, assuming that bank m is in such a state that given co mmand is allowable). exceptions are covered in the notes below. 3. current state definitions: 3a. the read with auto precharge enabled or write with auto precharge enabled states can each be broken into two pa rts: the access period and th e precharge period. for read with auto precharge, the precharge period is defined as if the same burst were executed with auto precharge disabled and then fo llowed with the earl iest possible precharge command that still accesses all of the data in the burst. for write with auto precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge were dis- abled. the access period starts with registration of the command and ends where the pre- charge period (or t rp) begins. table 11: truth table ? current state bank n ? command to bank m notes 1?6 apply to all states listed in this table; the other referenced notes appear below and on next page current state cs# ras# cas# we# command (action) notes any hxxx deselect (nop/continu e previous operation) lhhh no operation (nop/conti nue previous operation) idle xxxx any command otherwise allowed to bank m row activating,active, or precharging llhh active (select and activate row) lhlh read (select column and start read burst) 7 lhl l write (select column and start write burst) 7 llhl precharge read (auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start new read burst) 7 lhl l write (select column and start write burst) 7, 9 llhl precharge write (auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 10 lhl l write (select column an d start new write burst) 7 llhl precharge read (with auto precharge) llhh active (select and activate row) lhlh read (select column and start new read burst) 3a, 7 lhl l write (select column and start write burst) 3a, 7 llhl precharge write (with auto precharge) llhh active (select and activate row) lhlh read (select column and start read burst) 3a,7 lhl l write (select column an d start new write burst) 3a,7 llhl precharge idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 55 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram operations this device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled, any command to other banks is sup- ported, as long as that command does not inte rrupt the read or write data transfer already in process. in either case, all other related limitations apply (that is, contention between read data and write data must be avoided). 3b. the minimum delay from a re ad or write command with auto precharge enabled to a command to a different ba nk is summarized below. cl ru = cas latency (cl) rounded up to the next integer; bl = burst length 4. auto refresh and load mode register commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and se q uences not shown are illegal or reserved. 7. reads or writes listed in the command (action) column include reads or writes with auto precharge enabled and reads or wr ites with auto precharge disabled. 8. re q uires appropriate dm masking. 9. a write command may be appl ied after the completion of the read burst; otherwise, a burst terminate must be used to end the read burst prior to asserting a write com- mand. 10. a read command may be applied after the co mpletion of the writ e burst; otherwise, a burst terminate must be used to end th e write burst prior to asserting a read command. from command to command minimum delay (with concurrent auto precharge) write (with auto precharge) read or read (with auto precharge) [1 + (bl/2)] t ck + t wtr write or write (with auto precharge) (bl/2) t ck precharge 1 t ck active 1 t ck read (with auto precharge) read or read (with auto precharge) (bl/2) t ck write or write (with auto precharge) [cl ru + (bl/2)] t ck precharge 1 t ck active 1 t ck
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 56 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram electrical specifications electrical specifications absolute maximum ratings stresses greater than those listed in table 12 may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to abso lute maximum rating conditio ns for extended periods may affect reliability. table 12: absolute maximum ratings symbol parameter min max unit v dd v dd supply voltage relative to v ss ?0.3 2.7 v v dd q v dd q supply voltage relative to v ss ?0.3 2.7 v v in , v out voltage on any pin relative to v ss ?0.3 2.7 v t stg storage temperature ?55 +150 c table 13: electrical characteristics and operating conditions notes 1?5 on pages 52 and 53 apply to all parameters in this table; see other in dicated notes on pages 63?65 v dd /v dd q = 1.70?1.95v parameter/condition symbol min max unit notes supply voltage v dd 1.70 1.95 v 26, 29 i/o supply voltage v dd q 1.70 1.95 v 26, 29 address and command inputs input high voltage v ih 0.8 v dd qv dd q + 0.3 v 21, 28 input low voltage v il ?0.3 0.2 v dd qv21, 28 clock inputs (ck, ck#) dc input voltage v in ?0.3 v dd q + 0.3 v22 dc input differ ential voltage v id ( dc ) 0.4 v dd qv dd q + 0.6 v7,22 ac input differ ential voltage v id ( ac ) 0.6 v dd qv dd q + 0.6 v7,22 ac differential crossing voltage v ix 0.4 v dd q 0.6 v dd q v 8, 22 data inputs dc input high voltage v ih ( dc ) 0.7 v dd qv dd q + 0.3 v 21, 23, 28 ac input high voltage v ih ( ac ) 0.8 v dd qv dd q + 0.3 v 21, 23, 28 dc input low voltage v il ( dc ) ?0.3 0.3 v dd q v 21, 23, 28 ac input low voltage v il ( ac ) ?0.3 0.2 v dd q v 21, 23, 28 data outputs dc output high vo ltage: logic 1 (i oh = ?0.1ma) v oh 0.9 v dd q? v27 dc output low voltage: logic 0 (i ol = 0.1ma) v ol ? 0.1 v dd qv 27 leakage current input leakage current any input 0v v in v dd (all other pins not under test = 0v) i i ?1 1 a output leakage current (dq are disabled; 0v v out v dd q) i oz ?5 5 a operating temperature commercial t a 0+70c industrial t a ?40 +85 c
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 57 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram electrical specifications table 14: capacitance (x16, x32) note 41 on page 65 applies to all parameters in this table; notes appear on pages 63?65 parameter symbol min max units notes delta input/output capa citance: dq, dqs, dm dc io ?0.50pf17 delta input capacitance: command and address dc c i1 ?0.50pf delta input capacitance: ck, ck# dc i2 ?0.25pf input/output capacitance: dq, dqs, dm c io 2.0 4.5 pf input capacitance: command and address c i 1 1.5 3.0 pf input capacitance: ck, ck# c i 2 1.5 3.5 pf input capacitance: cs#, cke c i 3 1.5 3.0 pf
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 58 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram electrical specifications table 15: i dd specifications and conditions (x16) notes: 1?5, 9, 11 apply to all parameters in this table; notes appear on pages 63?65; v dd /v dd q = 1.70?1.95v parameter/condition symbol max units notes -6 -75 operating one bank active-precharge current : t rfc = t rfc (min); t ck = t ck (min); cke = high; cs = high between va lid commands; address inputs are switching every two clock cycles; data bus inputs are stable i dd 0 60 55 ma 16 precharge power-down standby current : all banks idle; cke is low; cs is high, t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd 2p standard 300 300 a 36 i dd 2p low power 220 220 36 precharge power-down standby current with clock stopped : all banks idle; cke is low; cs is high, ck = low, ck# = high; address and control inputs are switching; data bus inputs are stable i dd 2ps standard 300 300 a 36 i dd 2ps low power 220 220 36 precharge non-power-down standby current : all banks idle; cke = high; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd 2n 25 20 ma precharge non-power-down standby current with clock stopped : all banks idle; cke = high; cs = high; ck = low; ck# = high; address and control inputs are switching; data bus inputs are stable i dd 2ns 55ma active power-down standby current : one bank active; cke = low; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd 3p 55ma active power-down standby current with clock stopped : one bank active; cke = low; cs = high; ck = low; ck# = high; address and control inputs are switching; data bus inputs are stable i dd 3ps 33ma active non-power-down standby current : one bank active; cke = high; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd 3n 25 20 ma 16 active non-power-down standby current with clock stopped : one bank active; cke = high; cs = high; ck = low; ck# = high; address and control inputs are swit ching; data bus inputs are stable i dd 3ns 10 10 ma 16 operating burst read : one bank active; bl = 4; cl = 3; t ck = t ck (min); continuous read bursts; i out = 0ma; address inputs are switching every two clock cycles; 50 percent data changing each burst i dd 4r 100 95 ma 16 operating burst write : one bank active; bl = 4; t ck= t ck (min); continuous write bursts; address inputs are switching; 50 percent data changing each burst i dd 4w 100 100 ma 16 auto refresh current : burst refresh; cke = high; address and control inputs are switching; data bus inputs are stable t rfc = t rfc (min) i dd 5 65 60 ma t rfc = t refi i dd 5a 33ma20 deep power-down current : address and control inputs are stable; data bus inputs are stable i dd 8 10 10 a 36, 38
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 59 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram electrical specifications table 16: i dd specifications and conditions (x32) notes: 1?5, 9, 11 apply to all parameters in this table; notes appear on pages 63?65; v dd /v dd q = 1.70?1.95v parameter/condition symbol max units notes -6 -75 operating one bank active-precharge current : t rfc = t rfc (min); t ck = t ck (min); cke = high; cs = high between valid commands; address inputs are switching every two clock cycles; data bus inputs are stable jedec-standard option i dd 0 80 65 ma 16, 36 reduced page-size option i dd 0 70 55 ma 16, 35 precharge power-down standby current : all banks idle; cke is low; cs is high, t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd 2p standard 300 300 a 36 i dd 2p low power 220 220 36 precharge power-down standby current with clock stopped : all banks idle; cke is low; cs is high, ck = low, ck# = high; address and control inputs are switching; data bus inputs are stable i dd 2ps standard 300 300 a 36 i dd 2ps low power 220 220 36 precharge non-power-down standby current : all banks idle; cke = high; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd 2n 25 20 ma precharge non-power-down standby current with clock stopped : all banks idle; cke = high; cs = hi gh; ck = low; ck# = high; address and control inputs are switching; data bus inputs are stable i dd 2ns 55ma active power-down standby current : one bank active; cke = low; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd 3p 55ma active power-down standby current with clock stopped : one bank active; cke = low; cs = high; ck = low; ck# = high; address and control inputs are switching; data bus inputs are stable i dd 3ps 33ma active non-power-down standby current : one bank active; cke = high; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd 3n 25 20 ma 16 active non-power-down standby current with clock stopped : one bank active; cke = high; cs = high; ck = low; ck# = high; address and control inputs are switching; data bus inputs are stable i dd 3ns 10 10 ma 16 operating burst read : one bank active; bl = 4; cl = 3; t ck = t ck (min); i out = 0ma; address inputs are switching every two clock cycles; 50 percent data changing each burst i dd 4r 135 115 ma 16 operating burst write : one bank active; bl = 4; t ck = t ck (min); address inputs are switching; 50 percent data changing each burst jedec-standard option i dd 4w 160 140 ma 16, 36 reduced page-size option i dd 4w 140 120 ma 16, 35 auto refresh current : burst refresh; cke = high; address and control inputs are switching; data bus inputs are stable t rc = t rfc (min) i dd 5 65 60 ma t rc = t refi i dd 5 a3 3ma 20 deep power-down current : address and control inputs are stable; data bus inputs are stable i dd 8 10 10 a 36, 38
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 60 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram electrical specifications figure 36: typical self refresh current vs. temperature (x16, x32) table 17: i dd 6 specifications and conditions (x16, x32) notes: 1?5, 9, 10, 36, and 39 appl y to all parameters in this tabl e; notes appear on pages 63?65; v dd /v dd q = 1.70?1.95v parameter/condition symbol low i dd 6 option ?l? standard i dd 6 option units self refresh current : cke = low; t ck = t ck (min); address and control inputs are stable; data bu s input are stable full array, 85c i dd 6a 220 300 a full array, 70c i dd 6b 175 210 a full array, 45c i dd 6c 140 190 a full array 15c i dd 6d 125 180 a half array, 85c i dd 6a 200 275 a half array, 70c i dd 6b 150 180 a half array, 45c i dd 6c 130 160 a half array, 15c i dd 6d 115 150 a 1/4 array, 85c i dd 6a 185 265 a 1/4 array, 70c i dd 6b 140 160 a 1/4 array, 45c i dd 6c 120 140 a 1/4 array, 15c i dd 6d 115 140 a 1/8 array, 85c i dd 6a 175 255 a 1/8 array, 70c i dd 6b 125 150 a 1/8 array, 45c i dd 6c 115 130 a 1/8 array, 15c i dd 6d 110 125 a 1/16 array, 85c i dd 6a 170 250 a 1/16 array, 70c i dd 6b 120 140 a 1/16 array, 45c i dd 6c 110 120 a 1/16 array, 15c i dd 6d 105 115 a ?40 ?30 ?20 ?10 0 10 20 30 40 50 6 0 70 80 90 temperature ( c ) c urrent (a) 150 125 100 75 50 25 0 full array half array 1/4 array 1/8 array 1/1 6 array
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 61 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram electrical specifications table 18: electrical characteristics and recommended ac operating conditions notes: 1?6, 22 apply to all parameters in this table; no tes appear on pages 63?65; v dd /v dd q = 1.70?1.95v parameter symbol -6 -75 units notes min max min max access window of dq from ck/ck# cl = 3 t ac(3) 2.0 5.0 2.0 6.0 ns cl = 2 t ac(2) 2.0 6.5 2.0 6.5 ck high-level width t ch 0.45 0.55 0.45 0.55 t ck ck low-level width t cl 0.45 0.55 0.45 0.55 t ck clock cycle time cl = 3 t ck(3) 6 ? 7.5 ? ns 24 cl = 2 t ck(2) 12 ? 12 ? minimum t cke high/low time t cke 1 ? 1 ? t ck auto precharge write re covery + precharge time t dal ? ? ? ? 32 dq and dm input hold time relative to dqs t dh 0.5 ? 0.75 ? ns 19,23,31 dq and dm input setup time relative to dqs t ds 0.5 ? 0.75 ? ns 19,23,31 dq and dm input pulse width (for each input) t dipw 1.8 ? 1.8 ?ns 33 access window of dqs from ck/ck# cl = 3 t dqsck(3) 2.0 5.0 2.0 6.0 ns cl = 2 t dqsck(2) 2.0 6.5 2.0 6.5 dqs input high pulse width t dqsh 0.35 0.6 0.4 0.6 t ck dqs input low pulse width t dqsl 0.35 0.6 0.4 0.6 t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq ? 0.5 ? 0.6 ns 18, 19 write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 ? 0.2 ? t ck dqs falling edge from ck rising - hold time t dsh 0.2 ? 0.2 ? t ck data valid output window (dvw) n/a t qh - t dqsq t qh - t dqsq ns 18 half clock period t hp t ch, t cl ? t ch, t cl ?ns 24 data-out high-z window from ck/ck# cl = 3 t hz(3) ? 5.0 ? 6.0 ns 12, 30 cl = 2 t hz(2) ? 6.5 ? 6.5 ns data-out low-z window from ck/ck# t lz 1.0 ? 1.0 ? ns 12, 30 address and control input ho ld time (fast slew rate) t ih f 1.1 ? 1.3 ? ns 11 address and control input se tup time (fast slew rate) t is f 1.1 ? 1.3 ? ns 11 address and control input ho ld time (slow slew rate) t ih s 1.2 ? 1.5 ? ns 11 address and control input se tup time (slow slew rate) t is s 1.2 ? 1.5 ? ns 11 address and control input pulse width t ipw 2.6 ? 2.6 ?ns 33 load mode register command cycle time t mrd 2 ? 2 ? t ck dq?dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs ? t hp - t qhs ? ns 18, 19 data hold skew factor t qhs 0.65 ? 0.75 ns active-to-precharge command t ras 42 70,000 45 70,000 ns 25 active-to-active or active-to-auto refresh command period t rc 60 ? 75 ? ns active-to-read or write delay t rcd 18 ? 22.5 ? ns refresh period t ref ? 64 ? 64 ms average periodic refresh interval (x16) t refi ? 7.8 ? 7.8 s 37 average periodic refresh interval (x32) t refi ? 15.6 ? 15.6 s 37 auto refresh command period t rfc 70 ? 70 ? ns precharge command period t rp 18 ? 22.5 ? ns
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 62 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram electrical specifications dqs read preamble cl = 2 t rpre(2) 0.5 1.1 0.5 1.1 t ck cl = 3 t rpre(3) 0.9 1.1 0.9 1.1 dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 12 ? 15 ? ns dqs write preamble t wpre 0.25 ? 0.25 ? t ck dqs write preamble setup time t wpres 0 ? 0 ? ns 14, 15 dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck 13 write recovery time t wr 12 ? 15 ? ns 40 internal write to read command delay t wtr 1 ? 1 ? t ck exit power-down to first valid command t xp 1 ? 1 ? t ck exit self refresh to first valid command t xsr 120 ? 120 ? ns table 18: electrical characteristics and recomm ended ac operating conditions (continued) notes: 1?6, 22 apply to all parameters in this table; no tes appear on pages 63?65; v dd /v dd q = 1.70?1.95v parameter symbol -6 -75 units notes min max min max
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 63 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram notes notes 1. all voltages referenced to v ss . 2. all parameters assume proper device initialization. 3. tests for ac timing, i dd , and electrical ac and dc ch aracteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 4. outputs measured with equivalent load; transmission line delay is assumed to be very small: 5. timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v dd q/2 (or to the crossing point for ck/ck#). the output timing refere nce voltage level is v dd q/2. 6. all ac timings assume an input slew rate of 1v/ns. 7. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 8. the value of v ix is expected to equal v dd q/2 of the transmitting device and must track variations in the dc level of the same. 9. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time at cl = 3 for -6 and cl = 3 for -75 with the outputs open. 10. enables on-chip refresh and address counters. 11. fast command/ad dress input slew rate 1 v/ns. slow command/ address input slew rate 0.5 v/ns. if the slew rate is less than 0.5 v/ns, timing must be derated: t is has an additional 50ps per each 100 mv/ns reduct ion in slew rate from the 0.5 v/ns. t ih remains constant. if the slew rate exce eds 4.5 v/ns, functionality is uncertain. 12. t hz and t lz transitions occur in the same access time windows as data valid transi- tions. these parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (hz) or begins driving (lz). 13. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, bu t system performance (bus turnaround) will degrade accordingly. 14. this is not a device limit. the device will operate with a negative value, but system performance (bus turnaround) will degrade accordingly. 15. it is recommended that dqs be valid (high or low) on or before the write com- mand. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. i/o 20pf i/o 10pf full-drive strength one-half-drive strength i/o 5pf i/o 2.5pf quarter-drive strength one-eighth-drive strength z 0 = 50 z 0 = 50 z 0 = 50 z 0 = 50
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 64 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram notes 16. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. 17. the i/o capacitance per dqs and dq byte/group will not differ by more than this maximum amount for any given device. 18. the data valid window is deri ved by achieving other specifications: t hp ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates in direct propor- tion to the clock duty cycle, and a practical data valid window can be derived. the clock is allowed a maximum duty cycle vari ation of 45/55. functionality is uncertain when operating beyond a 45/55 ratio. 19. referenced to each output group: for x16, ldqs with dq0?dq7; and udqs with dq8?dq15. for x32, dqs0 with dq0?dq7; dq s1 with dq8?dq15; dqs2 with dq16? dq23; and dqs3 with dq24?dq31. 20. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period ( t rfc [min]) else cke is low (for example, during standby). 21. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through to the target ac level, v il ( ac ) or v ih ( ac ). b. reach at least the target ac level. c. after the ac target level is reached, co ntinue to maintain at least the target dc level, v il ( dc ) or v ih ( dc ). 22. ck and ck# input slew rate must be 1 v/ns (2 v/ns if measured differentially). 23. dq and dm input slew rates must not deviate from dqs by more than 10 percent. if the dq/dm/dqs slew rate is less than 0.5 v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100 mv/ns reduction in slew rate. if slew rate exceeds 4 v/ns, functi onality is uncertain. 24. t hp (min) is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs, collectively. 25. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satisfied prior to the intern al precharge command being issued. 26. any positive glitch must be less than 1/3 of the clock cycle and not more than +200mv or 2.0v, whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either ?150mv or 1.6v, whichever is more positive. 27. the voltage levels used are derived from a minimum v dd level and the referenced test load. in practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 28. v ih overshoot: v ih (max) = v dd q + 1.0v for a pulse width 3ns, and the pulse width cannot be greater than 1/3 of the cycle rate. v il undershoot: v il (min) = ?1.0v for a pulse width 3ns, and the pulse width cannot be greater than 1/3 of the cycle rate. 29. v dd and v dd q must track each other, and v dd q must be less than or equal to v dd . 30. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. 31. the transition times for input sign als (cas#, cke, cs#, dm, dq, dqs, ras#, we#, and addresses) are measured between v il ( dc ) and v ih ( ac ) for rising input signals and between v ih ( dc ) and v il ( ac ) for falling input signals. 32. t dal = ( t wr/ t ck) + ( t rp/ t ck): for each term, if not already an integer, round to the next higher integer. 33. these parameters guarantee device timing, but are not tested on each device. 34. clock must be toggled a minimum of two times during this period.
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 65 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram notes 35. reduced page-size option (a12). see page 1. 36. current may be slightly higher for up to 500ms when entering this operating mode. 37. the maximum t refi value applies to both a11 an d a12 row size ordering options. 38. deep power-down current is nominal value at 25c. the parameter is not tested. 39. the values for i dd 6 85c are 100 percent tested. valu es for 70c, 45c, and 15c are sampled only. 40. at least one clock cycle is required during t wr time when in auto-precharge mode. 41. this parameter is sampled. v dd /v dd q = 1.70?1.95v, f = 100 mhz, t a = 25c, v out (dc) = v dd q/2, v out (peak-to-peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in load- ing.
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 66 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram timing diagrams timing diagrams figure 37: data output timing ? t dqsq, t qh, and data valid window (x16) notes: 1. dq transitioning afte r dqs transitions defines the t dqsq window. ldqs defines the lower byte, and udqs defines the upper byte. 2. dq0, dq1, dq2, dq3, dq4, dq5, dq 6, or dq7. 3. t dqsq is derived at each dqs clock edge and is not cumulative over time and begins with dqs transition and ends with the last valid dq transition. 4. t qh is derived from t hp: t qh = t hp - t qhs. 5. t hp is the lesser of t cl or t ch clock transition collectively when a bank is active. 6. the data valid window is derived for each dqs transition and is defined as t qh - t dqsq. 7. dq8, dq9, dq10, dq11, dq 12, dq13, dq14, or dq15. dq (last data valid) 2 dq 2 dq 2 dq 2 dq 2 dq 2 dq 2 ldqs 1 dq (last data valid) 2 dq (first data no longer valid) 2 dq (first data no longer valid) 2 dq0?dq7 and ldqs, collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n ck ck# t1 t2 t3 t4 t2n t3n t qh 4 t qh 4 t dqsq 3 t dqsq 3 t dqsq 3 t dqsq 3 data valid window data valid window dq (last data valid) 7 dq 7 dq 7 dq 7 dq 7 dq 7 dq 7 udqs 1 dq (last data valid) 7 dq (first data no longer valid) 7 dq (first data no longer valid) 7 dq8?dq15 and udqs, collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n t qh 4 t qh 4 t qh 4 t qh 4 t dqsq 3 t dqsq 3 t dqsq 3 t dqsq 3 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t qh 4 t qh 4 data valid window data valid window data valid window data valid window data valid window upper byte lower byte data valid window
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 67 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram timing diagrams figure 38: data output timing ? t dqsq, t qh, and data valid window (x32) notes: 1. dq transitioning afte r dqs transitions defines the t dqsq window. 2. byte 0 is dq[7:0]; byte 1 is dq[15:8]; byte 2 is dq[23:16]; byte 3 is dq[31:24]. 3. t dqsq is derived at each dqs clock edge and is not cumulative over time and begins with dqs transition and ends with the last valid dq transition. 4. t qh is derived from t hp: t qh = t hp - t qhs. 5. t hp is the lesser of t cl or t ch clock transition collectively when a bank is active. 6. the data valid window is derive d for each dqs transition and is t qh - t dqsq. dq (last data valid) 2 dq 2 dq 2 dq 2 dq 2 dq 2 dq 2 dqm0/dqm1/dqm2/dqm3 dq (last data valid) 2 dq (first data no longer valid) 2 dq (first data no longer valid) 2 dq and dqs collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n ck ck# t1 t2 t3 t4 t2n t3n t qh 4 t qh 4 t dqsq 3 t dqsq 3 t dqsq 3 t dqsq 3 data valid window data valid window t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t qh 4 t qh 4 data valid window data valid window byte 0 byte 1 byte 2 byte 3
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 68 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram timing diagrams figure 39: data output timing ? t ac and t dqsck notes: 1. dq transitioning af ter dqs transition define t dqsq window. 2. all dq must transition by t dqsq after dqs transitions, regardless of t ac. 3. t ac is the dq output window relative to ck and is the long-term component of dq skew. 4. shown with cl = 3. figure 40: data input timing notes: 1. t dsh (min) generally occurs during t dqss (min). 2. t dss (min) generally occurs during t dqss (max). 3. write command issued at t0. 4. for x16, ldqs controls the lower byte, and udqs controls the upper byte. for x32, dqs0 controls dq[7:0], dqs1 controls dq[15:8], dq s2 controls dq[23:16], and dqs3 controls dq[31:24]. 5. for x16, ldm controls the lower byte, and ud m controls the upper byte. for x32, dm0 con- trols dq[7:0], dm1 controls dq[15:8]5, dm2 controls dq [23:16], and dm3 controls dq[31:24]. ck ck# dqs or ldqs/udqs 1 t 0 t1 t 2 t 3 t4 t5 t2n t 3 n t4n t5n t6 t rpst t rpre t hz (max) command nop nop nop nop t dqsck (max) nop all dq values, collectively 2 t3 t2n t2 t3n t4n t5n t4 t5 t ac (max) cl = 3 nop read t dqsck (max) t dq ss t dq s h t wp s t t dh t d s t dq s l t d ss 2 t d s h 1 t d s h 1 t d ss 2 c k c k# t0 3 t1 t1n t2 t2n t3 d in b don ? t c are transitionin g d ata t wpre t wpre s dq s 4 dq 5 dm 6
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 69 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram timing diagrams figure 41: initialize and load mode registers notes: 1. pre = precharge command; lmr = load mode register command; ar = auto refresh command; act = active co mmand; ra = row address; ba = bank address. 2. nop or deselect commands are re q uired for at least 200s. 3. other valid commands are possible. 4. nop or deselect commands are re q uired during this time. cke lvcmos high level dq bank address (ba0, ba1) load standard mode register load extended mode register t mrd 4 t mrd 4 t rfc 4 t rfc 4 power-up: v dd and ck stable t = 200s high-z dm dqs high-z addresses ra a10 ra ck ck# t ch t cl t ck v dd v dd q command 1 lmr nop lmr ar t is t ih ba0 = l, ba1 = l t is t ih ba0 = l, ba1 = h t is t ih code code t is t ih code code pre all banks t is t ih t0 t1 ta0 tb0 tc0 td0 te0 tf0 don?t care ba ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp 4 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop 2 ar act ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop 3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ( ) )
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 70 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram timing diagrams figure 42: power-down mode (active or precharge) notes: 1. if this command is a precharge (or if the device is already in th e idle state), then the power-down mode shown is precharge power-down . if this command is an active (or if at least one row is already active ), then the power-down mode shown is active power-down. 2. no column accesses are allowed to be in progress at the time power-down is entered. 3. there must be at least one clock pulse during t xp time. c k c k# c omman d valid 1 nop a dd ress c ke dq dm dq s nop t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih enter power- d own mo d e 2 exit power- d own mo d e 3 must not ex c ee d refresh d evi c e limits ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t 0 t1 ta0 ta1 ta2 t2 nop don ? t c are ( ) ( ) ( ) ( ) valid ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) tb1 valid valid t xp 3
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 71 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram timing diagrams figure 43: auto refresh mode notes: 1. pre = precharge; act = ac tive; ar = auto refresh; ra = row address; ba = bank address. 2. nop commands are shown for ease of illustra tion; other valid commands may be possible at these times. cke must be active during clock positive transitions. 3. nop or command inhibit are the on ly commands allowed until after t rfc time; cke must be active during cloc k positive transitions. 4. ?don?t care? if a10 is high at this point; a10 must be high if more than one bank is active (for example, must precharge all active banks). 5. dm, dq, and dqs signals are all ?don ?t care?/high-z for operations shown. 6. the second auto refresh is not re q uired and is only shown as an example of two back-to- back auto refresh commands. c k c k# c omman d 1 valid valid nop 2 pre c ke ra a0?a9, a11, a12 1 a10 1 ba0, ba1 1 bank(s) 4 ba ar ar 6 a c t one b ank all b anks c k t c h t c l t i s t i s t ih t ih t i s t ih ra ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ) ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ) ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq 5 dm 5 dq s 5 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rf c 6 t rp t rf c t0 t1 t2 t3 t4 ta0 t b 0 ta1 t b 1 t b 2 don ? t c are ) ) ( ) ( ) nop 2 nop 2 nop 2 nop 2, 3 nop 2, 3
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 72 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram timing diagrams figure 44: self refresh mode notes: 1. clock must be stable, cyclin g within specifications by ta0, before exiting self refresh mode. 2. device must be in the all banks idle sta te prior to entering self refresh mode. 3. nops or deselect is re q uired for t xsr time with at least two clock pulses. 4. ar = auto refresh command. 5. cke must remain low to rema in in self refresh mode. c k 1 c k# c omman d 4 nop ar a dd ress c ke 1 valid dq dm dq s valid nop t rp 2 t c h t c l t c k t i s t x s r 3 t i s t ih t i s t i s t ih t ih t i s enter self refresh mo d e exit self refresh mo d e ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t b 0 ta1 ( ) ( ) ( ) ( ) ( ) ( ) don ? t c are ( ) ( ) ( ) ( ) ta0 1
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 73 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram timing diagrams figure 45: bank read ? without auto precharge notes: 1. d out n = data-out from column n . 2. bl = 4 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a10 is high at t5. 5. pre = precharge, act = active, ra = row address, and ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. the precharge command can only be applied at t5 if t ras minimum is met. ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t ih t is t ih t is t ih t is t ih t is t ih ra t rcd t ras 7 t rc t rp cl = 2 dm t0 t1 t2 t3 t4 t5 t5n t6n t6 t7 t8 dq 1 dqs case 1: t ac (min) and t dqsck (min) case 2: t ac ( max) and t dqsck ( max) dq 1 dqs t hz ( max) nop 6 nop 6 command 5 3 act ra ra col n read 2 bank x ra ra ra bank x act bank x nop 5 nop 6 nop 6 don?t care transitioning data a0?a9 a11?a i 9 pre 7 bank x 4 t rpre t rpre t ac ( max) all banks one bank d out n d out n + 1 d out n + 2 d out n + 3 d out n d out n + 1 d out n + 2 d out n + 3 t lz (min) t lz (min) t dqsck (min) t ac (min) t rpst t rpst t dqsck (max)
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 74 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram timing diagrams 8. refer to figures 37 and 38 on pages 6 6?67 for dqs and dq timing details. figure 46: bank read ? with auto precharge notes: 1. d out n = data-out from column n . 2. bl = 4 in the case shown. 3. enable auto precharge. 4. ?don?t care? if a10 is high at t5. 5. pre = precharge; act = active; ra = row address; ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. c k c k# c ke a10 ba0, ba1 t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih t ih t i s t ih ra t r c d t ra s t r c t rp c l = 2 dm t0 t1 t2 t3 t4 t5 t5n t 6 n t 6 t7 t8 dq 1 dq s c ase 1: t a c ( min) an d t dq sc k ( min) c ase 2: t a c ( max) an d t dq sc k ( max) dq 1 dq s t hz ( max) nop 6 nop 6 c omman d 5 3 a c t ra ra c ol n read 2 bank x ra ra ra bank x a c t bank x nop 6 nop 6 nop 6 don ? t c are transitionin g d ata a0?a9 a11, a12 nop 6 t rpre t dq sc k ( max) t a c ( max) d out n d out n + 1 d out n + 2 d out n + 3 d out n d out n + 1 d out n + 2 d out n + 3 t dq sc k ( min) t a c ( min) t rp s t t lz ( min) t rpre t rp s t t lz ( min)
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 75 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram timing diagrams 7. refer to figures 37 and 38 on pages 6 6?67 for dqs and dq timing details. figure 47: bank write ? without auto precharge notes: 1. d in n = data-in from column n ; subse q uent elements are provided in the programmed order. 2. bl = 4 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a10 is high at t5. 5. pre = precharge; act = active; ra = row address; ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. t dsh is applicable during t dqss (min) and is referenced from ck t4 or t5. 8. t dss is applicable during t dqss (min) and is referenced from ck t5 or t6. c k c k# c ke a10 ba0, ba1 t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih t ih t i s t ih ra t rp t wr t0 t1 t2 t3 t4 t5 t5n t 6 t7 t8 t4n nop 6 nop 6 c omman d 5 3 a c t ra ra c ol n write 2 nop 6 one b ank all b anks bank x pre bank x nop 6 nop 6 nop 6 t dq s l t dq s h t wp s t bank x 4 dq 1 dq s dm d out b t d s t dh t dq ss (nom) t wpre t wpre s a0?a9 a11, a12 don ? t c are transitionin g d ata t ra s t r c d
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 76 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram timing diagrams figure 48: bank write ? with auto precharge notes: 1. d in n = data-in from column n ; subse q uent elements are provided in the programmed order. 2. bl = 4 in the case shown. 3. a10 = high, enable auto precharge. 4. act = active; ra = row address; ba = bank address. 5. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 6. t dsh is applicable during t dqss (min) and is referenced from ck t4 or t5. 7. t dss is applicable during t dqss (min) and is referenced from ck t5 or t6. c k c k# c ke a10 ba0, ba1 t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih t ih t i s t ih ra t r c d t ra s t rp t wr t0 t1 t2 t3 t4 t5 t5n t 6 t7 t8 t4n nop 5 nop 5 c omman d 4 3 a c t ra ra c ol n write 2 nop 5 bank x nop 5 bank x nop 5 nop 5 nop 5 t dq s l t dq s h t wp s t dq 1 dq s dm di b t d s t dh t dq ss (nom) don ? t c are transitionin g d ata t wpre s t wpre a0?a9 a11, a12
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 77 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram timing diagrams figure 49: write ? dm operation notes: 1. d in n = data-in from column n ; subse q uent elements are provided in the programmed order. 2. bl = 4 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a10 is high at t5. 5. pre = precharge; act = active; ra = row address; ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. t dsh is applicable during t dqss (min) and is referenced from ck t4 or t5. 8. t dss is applicable during t dqss (min) and is referenced from ck t5 or t6. c k c k# c ke a10 ba0, ba1 t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih t ih t i s t ih ra t r c d t ra s t rp t wr t0 t1 t2 t3 t4 t5 t5n t 6 t7 t8 t4n nop 6 nop 6 c omman d 5 3 a c t ra ra c ol n write 2 nop 6 one b ank all b anks bank x pre bank x nop 6 nop 6 nop 6 t dq s l t dq s h t wp s t bank x 4 dq 1 dq s dm d out b t d s t dh don ? t c are transitionin g d ata t dq ss (nom) t wpre s t wpre a0?a9 a11, a12
pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 78 ?2005 micron technology, inc. all rights reserved. 256mb: x16, x32 mobile ddr sdram package dimensions package dimensions figure 50: 60-ball vfbga package note: all dimensions are in millimeters. micron logo to be lased ball a1 id substrate material: plastic laminate mold compound: epoxy novolac solder ball material: sac105 (98.5% sn, 1% ag, 0.5% cu) seating plane 0.65 0.05 dimensions apply to solder balls post-reflow. the pre-reflow balls are ?0.42 on ?0.4 smd ball pads. 0.1 a a 0.3 0.025 9 0.1 4.5 0.05 1.0 max 3.6 7.2 ball a1 id 0.8 typ 8 0.1 3.2 4 0.05 6.4 60x ?0.45 0.8 typ 9 8 7 3 2 1 a b c d e f g h j k
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits spec ified over the power supply an d temperature range set forth herein. although considered final, these specifications ar e subject to change, as furthe r product development and data characterization sometimes occur. 256mb: x16, x32 mobile ddr sdram package dimensions pdf: 09005aef82091978 / source: 09005aef8209195b micron technology, inc., reserves the right to change products or specifications without notice. mt46h16m16lf__2.fm - rev. h 6/08 en 79 ?2005 micron technology, inc. all rights reserved. figure 51: 90-ball vfbga package note: all dimensions are in millimeters. ball a1 id 1.0 max mold compound: epoxy novolac substrate material: plastic laminate solder ball material: sac105 (98.5% sn, 1%ag, 0.5% cu) 13 0.1 ball a1 id 9 8 7 3 2 1 a b c d e f g h j k l m n p r 0.8 typ 6.5 0.05 8 0.1 4 0.05 3.2 5.6 0.65 0.05 seating plane a 11.2 6.4 0.1 a 90x 0.45 dimensions apply to solder balls post- reflow. pre-reflow balls are ?0.42 on ?0.4 smd ball pads. 0.8 typ

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